Generally, manufacturing/fabrication of an IC device includes processing of its design data, which includes physical layout Information of structures such as circuit (e.g., transistors) and interconnecting elements that would form the device, where the data may be provided by a client, or its IC designers, to an IC manufacturing vendor. Typically, a photolithography (lithography) process may be utilized to optically print/pattern various layers of a circuit design onto a surface of a silicon (Si) substrate for creating the various elements and circuits. In lithography, a photomask is used to mask or expose areas on the substrate that are to be, respectively, blocked from or patterned by a light beam, such as light produced by an Argon-Fluoride laser (ArF), Krypton-Fluoride laser (KrF), extreme ultraviolet (EUV), or the like source.
A photomask may be developed by use of electron beam (e-beam) lithography, which enables patterning/writing very small patterns on substrates with a high level of precision. Unfortunately, optical proximity effects, along with mask pattern fidelity and photoresist processing limitations commonly cause errors in patterning the desired pattern onto the substrate. To increase viable resolution and pattern transfer reliability, resolution enhancement techniques such as optical proximity correction (OPC) models may be utilized to optimize a photomask for substrate processing. The object of OPC is to make systematic modifications to mask geometry to compensate for systematic errors. However, complex designs and continued efforts to miniaturize the IC devices present various limitations that may negatively impact the manufacturing processes and cause less throughput, less process margin, higher costs, lower yields, or the like issues.
FIG. 1A is a layout illustration of an example IC device. IC designers utilize various electronic design automation (EDA) software tools in designing and analyzing the circuits in an IC device. Additionally, the design tools are utilized to render a layout of the IC design targeting a specific technology node (e.g., 28 nm, 20 nm, 14 nm, etc.) Moreover, an IC manufacturer, or a third party vendor, may use EDA tools to evaluate a client's IC design data, in a graphic data system file (e.g., GDSII), for determining manufacturability of the IC based on the manufacturer's production processes criteria and identifying any potential issues therein. Diagram 101 illustrates a layout of different layers in an IC device where a potential critical area 103 is highlighted and shown in greater detail as diagram 105 in FIG. 1B. As noted, e-beam lithography and OPC may be impacted by an IC design and its layout; therefore, criteria, such as minimum spacing between elements, associated with the lithography and/or OPC may be utilized to identify potential critical areas in the layout. However, potential bridging (e.g., short circuiting) issues exist with the current solution even after new OPC re-targeting. In diagram 105, a metal segment 107, such as in a second level metal layer, and two adjacent metal segments 109 and 111 are connected, respectively, to connecting vias 113a, 113b, and 113c, which are between a first level metal layer segment and a second level metal layer segment. As a short-term solution, the spacing between connecting vias may be formed at an angle of 45 degrees (45°), as shown in FIG. 1B, to increase the spacing to protect from the bridging issue of the nearby connecting vias after lithography in substrate processing. As shown in diagram 117 of FIG. 1C, one potential issue may be due to insufficient distances, such as 115, between the patterns of the connecting vias 113a, 113b, and/or 113c, where bridges may be formed causing signal interference. Another potential issue may be due to at least one border of the connecting vias 113a, 113b, and 113c being at an angle of 45°, as 119 shown in FIG. 1C, which may increase run times for the associated e-beam lithography and OPC processes. Additionally, a border rendered at a 45° angle may have a distorted edge, as 121, which may require additional e-beam writer iterations to render a smoother edge 123 as shown in diagram 125 of FIG. 1D. Although some of the stated issues may be addressed before the design of an IC is finalized (e.g., by an IC designer), it would be challenging and inefficient since the processes employed by different IC manufactures vary. Moreover, a potential bridging may be due to process variations in fabrication of the IC devices. It is noted that the above issues are not limited to any particular metal or any specific connecting via layer and may be associated with all backend interconnection layers.
A need therefore exists for a methodology enabling identification and partial re-routing of selected areas, including potential critical areas, in a layout of an IC design and the resulting device.